1. Field of the Invention
The invention relates to a phase frequency detector, and more particularly to a phase frequency detector used in a digital PLL system.
2. Description of the Related Art
A PLL (phase locked loop) is an automatic control circuit system capable of tracking the frequency and phase of an input signal, and is widely utilized in the field of frequency synthesis, clock/data recovery, clock de-skewing, and the like. Typical PLLs may be substantially divided into analog PLLs (APLL) and digital PLLs (DPLL).
FIG. 1 is a block diagram showing the system architecture of a conventional digital PLL. The digital PLL includes a phase frequency detector (PFD) 100, a phase error quantizer 110, a digitally controlled oscillator (DCO) 120 and a frequency divider 130. The PFD 100 compares a feedback signal Fi and an input signal Fr, determines a phase error therebetween, and outputs a phase error signal according to the phase error. Typical phase error signal is composed of an UP signal and a DOWN signal. The values of and the time difference between the two signals may represent the magnitude of the phase error between the feedback signal Fi and the input signal Fr. The phase error quantizer 110 quantizes the magnitude of the phase error and outputs a count signal COUNT according to the signal values of the UP signal and the DOWN signal, and the time difference therebetween. The DCO 120 outputs an output signal Fo according to the magnitude of the count signal COUNT, and the output signal Fo is then fed back through the divider 130 to the PFD 100 as the feedback signal Fi.
FIG. 2 shows the circuit architecture of a conventional phase frequency detector (PFD), which is detailed in U.S. Pat. No. 5,963,058, whose content is incorporated herein by reference. The PFD includes two D-type flip-flops 200 and 210 for generating the UP signal and the DOWN signal according to the input signal Fr and the feedback signal Fi, respectively, and an AND gate 220 for resetting the two flip-flops 200, 210. The operation principle of the phase frequency detector will be described with reference to the timing chart of FIG. 3A. It is assumed that the devices of the PFD mentioned above are rising-edge triggered devices, and that the Fr signal leads the Fi signal. The flip-flop 200 outputs the UP signal with a high level upon change of the Fr signal. Sequentially, the flip-flop 210 outputs the DOWN signal with a high level upon change of the Fi signal. When the UP signal and the DOWN signal are both of high level, the AND gate 220 outputs a reset signal RESET for resetting the flip-flops 200 and 210. As a result, the UP signal and the DOWN signal both return to low level. The operation under the situation when the signal Fr lags behind the signal Fi can be similarly derived.
As is well known to those skilled in the art, the PFD in FIG. 2 suffers from the drawbacks of the so-called “dead zone” phenomenon, as well as limitations on the counting resolution of the PFD induced by the delay in the reset path (i.e., the AND gate 220 in FIG. 2). Please refer to FIG. 3B, which illustrates the counting resolution limitation of the PFD mentioned above. When the phase error between the input signal Fr and the feedback signal Fi is smaller than a clock signal, the quantizer cannot detect the phase error therebetween and thus is not able to obtain a count signal COUNT.